| 摘要 |
PURPOSE:To remove jitter, and to prevent differential phase(DP) deterioration at the time of return to an analog signal by reading picture element data written in a memory at a clock independent of the sampling frequency of a transmission side. CONSTITUTION:A timing circuit 102 to operate at the clock of a transmission side transmission line outputs the display pulse of an area where a PCM video signal is transmitted and the field period display pulse of a video signal, and a write address generation circuit 103 to operate at the similar clock counts up the display pulse of the area where the PCM video signal is transmitted, and this becomes an address, and the PCM video signal is written in a picture element memory 104. This memory 104 is read out similarly according to the clock of the sampling frequency to be outputted by a generation circuit 109 to generate the clock independent of a transmission side clock. Thus, the jitter is eliminated practically, and the DP deterioration at the time of the return to the analog signal by a D/A converter 110 can be prevented. |
