发明名称 LEAD PLATING METHOD FOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To prevent a solder from rising up and a soldered joint from deteriorating in strength even if the mounting or dismounting of an integrated circuit is performed due to a design change by a method wherein the whole lead is subjected to a nickel plating, and only the tip of the lead, which a solder adheres to, is Au-plated. CONSTITUTION:After the whole lead 3s have been Ni-plated, the lead 3s are brazed to connecting pad 33s, which are provided to a package of an integrated circuit 2, to be fixed to the integrated circuit 33s. Next, the integrated circuit 2 is positioned to a first cut-out 30a formed on a Au plating jig 30 which is formed of a plastic resin, whereby only the tips (where solder adheres actually) of the lead 3s are made to protrude from through-holes 31' of a mask 31. And, when the integrated circuit 2 package is positioned to a Au plating tank 32 which contains a molten electroless plating Au, only the tips of the lead 3s are Au-plated.</p>
申请公布号 JPH0215662(A) 申请公布日期 1990.01.19
申请号 JP19880165522 申请日期 1988.07.01
申请人 FUJITSU LTD 发明人 OCHIAI MASAYUKI;OTA HIDEKI
分类号 H05K3/34;H01L23/50 主分类号 H05K3/34
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