| 摘要 |
<p>PURPOSE:To attain octet multiplexing and bit multiplexing only by means of changing the content of a memory by setting to which signal among received signals multiframe phase control is executed, multiplexing and separating data signals and control signals in respective terminals based on information which has been set. CONSTITUTION:In a time division multiplexing device, the content of the memory is read at the bit speed of a line and by the time period of a multiframe. At the same time, the data signals and the control signals are fetched from the terminals through a terminal interface part. Next, a multiframe synchronous pattern is inserted into a synchronous pattern insertion means according to the content of the memory and a polarity conversion means transmits a signal adjusted to the polarity of an opposite device to the line. A phase synchronous means detects the pattern, edits the signal by logical buses and transmits the data signals and the control signals through the terminal interfaces. Thus, a clock generation part 5, plural terminal interface parts 6, the buses 7-9, a multiplexing conversion part 4 and a line interface part 3 are provided in the device 1.</p> |
