| 摘要 |
PURPOSE:To make grounded sections of a semiconductor substrate SB scattered inside an EPROM so as to decrease a substrate in a ground resistance of each memory cell without disturbing the arrangement of memory cell MCs in periodicity and to familitate the exclusion of hot holes by a method wherein the semiconductor substrate SB and a ground line GL are connected with each other by each memory unit cell MU. CONSTITUTION:Each memory cell MC is composed of an n-type source, an n-type drain D, a floating gate FG, and a control gate all formed on a p-type silicon substrate SB. A memory cell unit MU is composed of four memory cells (2X4=8) formed on a region which is surrounded with a line consisting of a single dot-line, and the above memory cell unit MUs are periodically arranged in matrix. The drain Ds belonging to the same column are connected with each other through the intermediary of drain contact DCs to constitute a bit line BL, and the n-type source Ss belonging to the same row are formed inside the n-type region RR and connected with each other. Moreover, the memory cell unit MUs are connected with grounding line GLs respectively. |
