| 摘要 |
PURPOSE:To sharply reduce a size of a memory cell by a method wherein a source region of two N-channel transistors is used jointly and polycrystalline silicon to be used as a VDD power supply line is formed and arranged, together with polycrystalline silicon of a lead element, on a partial region of the source region. CONSTITUTION:Polycrystalline silicon 22, 23 to be used as load elements of inverters constituting a memory cell are arranged on a MOS transistor; a power- supply line formed by stretching polycrystalline silicon 20 of a load element is arranged on a partial region of a jointly used source region of the MOS transistor of two inverters. A plane area of this polycrystalline silicon can be reduced from the memory cell. |
