| 摘要 |
<p>PURPOSE:To attain high speed of readout by providing a memory cell comprising a transistor (TR) pair whose gate is connected to a word line and a bit line pair of 2 line one pair in common, giving a ground potential to one bit line and giving a power potential to other bit line and detecting a difference voltage to the bit line pair. CONSTITUTION:Gates of 1st and 2nd TRs Q1, Q2 constituting each memory cell are connected in common to a word line WL, the bit line is constituted by it line pair of 2 line one pair, the source S of the 1st TR Q1 is connected to a ground potential VSS and the source S of the TR Q2 is connected to a power potential VDD. Then one bit line potential descends from an intermediate potential VMID to ground potential VSS and other bit line potential VMID rises from the intermediate potential to the power potential VDD, a potential difference is caused to the bit line pair and the potential difference is detected by a difference sense amplifier 5. Thus, the bit line potential is increased/decreased from the middle of the ground potential and the readout time is reduced.</p> |
