| 摘要 |
The semiconductor memory device has a dynamic random access to allow simultaneous clearing of all data. A number of memory cells are connected to respective BIT line pairs, a number of sense amplifiers, each having complementary signal terminals to one pair of BIT lines, and a pair of data buses for inputting and outputting data to and from a seleted BIT line. A data inverting circuit is operatively coupled to the data buses to selectively invert input/output data so that the charging states of respective cells connected to the lines of a respective pair are the same for the same input/output data.
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