发明名称 CLOCK CONTROL CIRCUIT
摘要 <p>PURPOSE:To easily execute the operation margin test of a logical circuit by changing the period and width of a clock to be supplied according to a micro- program. CONSTITUTION:A value to set the period of a pulse to a register 1 and a value to set the width of the pulse are set by a processor 9 or an initial setting circuit 7. A reference clock generating circuit 6 outputs a reference clock, whose period is 50ns, to a counter 2. The counter 2 counts the reference clock from the value, which is set in the register 1, and outputs the clock to a decoder 4. When a determined upper limit value 40 is inputted, the decoder 4 resets the value of the counter 2 to the value of the register 1. A comparing circuit 3 compares the value, which sets the pulse width to be set to the register 1, and the output value of the counter 2. When the output value goes to be larger, an 'H' is inputted to an FF5. The FF5 outputs the pulse to a logical circuit 10 in correspondence to the output of the comparing circuit 3.</p>
申请公布号 JPH0214309(A) 申请公布日期 1990.01.18
申请号 JP19880165508 申请日期 1988.07.01
申请人 FUJITSU LTD 发明人 SEKI KAZUHISA
分类号 G06F1/04;G06F1/08 主分类号 G06F1/04
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