| 摘要 |
PURPOSE:To speed up an operating frequency by giving an input/output signal of each flip-flop directly from a selection means not through a programmable wiring or the like causing much delay time. CONSTITUTION:Selection means 15, 16 for an input signal to flip-flops 13, 14 are provided and an output signal of an adjacent flip-flop is inputted through the said selection to connect the flip-flops in cascade. The flip-flop of the final stage of a programmable logic element receives its output signal through an exclusive connection line by the selection of a selection means of the 1st flip-flop of an adjacent programmable logic element similarly to attain mutual connection. The input/output signals of the flip-flops 13, 14 are connected together not through the input terminal of the programmable logic element or the programmable wiring with a large delay time in this way, then the operating frequency of the circuit realized by the connection of the flip-flops is quickened. |
