| 摘要 |
<p>Gate array LSI's are produced with the aid of a standard layout pattern defining a basic cell array region (2), on which internal cell arrays are arranged, and a peripheral circuit region (3), arranged on the periphery of the basic cell array region. The peripheral circuit region comprises input/output cell regions (7), for constructing an input buffer circuit and a part of an output circuit, and a general purpose cell array region (4) which can be used for constructing remaining parts of the output buffer circuit. Where the general purpose cell array region is not used in the construction of such a buffer circuit it can be used for constructing various other desired circuits. Thus greater design flexibility is made available.</p> |
