发明名称 PLL CIRCUIT
摘要 PURPOSE:To prevent a level difference from generating at the phase and frequency of an output signal in any case by comparing the output signal and applying a prescribed bias to the input side of a low pass filter when an abnormality is detected. CONSTITUTION:The title circuit provides a detecting means 6 to detect the abnormality of an output signal, a signal switching means 5 to input an output signal to a comparing means 1 in place of a reference signal 100 when an abnormality is detected by the detecting means 6 and a bias impressing means 7 to apply a prescribed bias to the input side of a low pass filter when at least the detecting means 6 detects the abnormality. When the abnormality is detected, the comparing means 1 compares the output signal, outputs the result of the phase difference zero to a low pass filter 2, a prescribed bias is applied to the input side of the low pass filter 2, the output is continuously changed and the central voltage to oscillate the fundamental frequency is obtained. Thus, the level difference does not occur at the phase and frequency of the output signal always in any case.
申请公布号 JPH0211022(A) 申请公布日期 1990.01.16
申请号 JP19880159473 申请日期 1988.06.29
申请人 TOSHIBA CORP 发明人 WATANABE SHINSUKE
分类号 H03L7/18;H03L7/14 主分类号 H03L7/18
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