发明名称 MEMORY LAYOUT FORMING METHOD
摘要 PURPOSE:To realize automatic formation by arranging a small-scale memory cell or decoder cell regularly in the vertical direction. CONSTITUTION:Four ROM/RAM cells and two decoder cells 7 are arranged with minimum spaces required such that the wirings 8 may be directed in the vertical direction of a semiconductor substrate, thus the ROM/RAM unit 4 of (aX4) words X b bits is realized. The size of the ROM/RAM designated by a user is input so as to determine the numbers of cells 6 and decoder cells 7 inside the unit 4, whereby the number of units required for realization of the size input is determined using this constituent unit so as to perform arrangement and wiring. By doing it in this way, the memory of an optional size can be automatically formed using a computer at the integration degree equivalent to the input design.
申请公布号 JPH0210767(A) 申请公布日期 1990.01.16
申请号 JP19880161818 申请日期 1988.06.28
申请人 MITSUBISHI ELECTRIC CORP 发明人 IIO KANAKO
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04;H01L27/10;H01L27/118 主分类号 H01L21/822
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