发明名称 SYNCHRONIZING LOGIC CIRCUIT
摘要 <p>PURPOSE:To easily synchronize operations by providing a circuit which determines a master or slave mode in accordance with the input signal of a terminal other than a reset terminal. CONSTITUTION:A synchronizing logic circuit is provided with a circuit which takes in the signal from a terminal LPEN at the time of reset. When the master mode will be set, an external multiplexer 8 is used to forcibly set the input from the terminal LPEN at the time of reset to '1'. By this operation, a signal 104 obtained by delaying an input 103 from the terminal LPEN is latched at the rise of reset to enter into the master mode. When the slave mode will be set, an external multiplexer 16 is used to forcibly set the input from the terminal LPEN at the time of reset to '0'. By this operation, a signal 113 obtained by delaying an input 112 from the terminal LPEN is latched at the fall of a reset signal 102 to enter into the slave mode.</p>
申请公布号 JPH0210418(A) 申请公布日期 1990.01.16
申请号 JP19880161476 申请日期 1988.06.28
申请人 NEC CORP 发明人 HIRASAWA MASAO
分类号 G06F15/177;G06F1/00;G06F1/24;G06F15/16 主分类号 G06F15/177
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