CIRCUIT SYNTHESIZING SYSTEM

摘要

PURPOSE: To form a stable variable delay line phase locked loop by providing first and second delay lines receiving common clock signals and delaying them by a selected period to first and second circuits and a phase detection means. CONSTITUTION: The clock signals CLKIN are supplied from an external clock source to CPU 10 and a floating point coprocessor FPC 20. In CPU 10, the signals CLKIN are delayed by the fixed period by a voltage control-type delay line VCDL 12. In FPC 20, the signals CLKIN are delayed by a period which can be controlled in response to a control signal by the voltage control-type delay line VCDL 22. The phase detection circuit 30 is connected to the first and second circuits, outputs the control signal 32 and generates potential related to a difference between the output signals. The signal 32 is added to VCDL 22 through a low pass filter LPF 37 and controls the delay time of VCDL 22.