| 摘要 |
PURPOSE:To eliminate noise pulse included in an output of a demodulation circuit by sampling sequentially the output of the demodulation circuit demodulating the FSK signal at 1st and 2nd flip-flops in response to the reference clock and latching the output of the demodulation circuit only when the outputs of the 1st and 2nd flip-flops are coincident. CONSTITUTION:The output of an arithmetic circuit 14 is inputted to a D flip-flop FF7 sampled by using an inverse of reference clock phi of the demodulation circuit 1, the output of the filp-flop FF7 is inputted to a D flip-flop FF8 and a 1st gate circuit A4 whose output is logical 1 when the both are logical 0 and a 2nd gate circuit A5 whose output is logical 1 when the both are logical 1 are provided and an output SR flip-flop 6 set/reset by the output of the two gate circuits A4, A5 is provided and the output is used as the demodulation output, then the stability of the demodulation output is obtained. |
