发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To improve reliability for a readout operation by setting a selective word line at an 'L' level at the time of performing the readout operation, and supplying a voltage of 'H' level with pulse width less than a readout cycle time on remaining word lines. CONSTITUTION:A NAND cell is constituted by connecting four memory cells M1-M4, and such NAND cells are arranged in matrix shape. The drain of the NAND cell is connected to a bit line BL via a first selective MOS transistor S, and the source to the ground via a second selective MOS transistor S. And when the readout operation is performed, by setting the voltage of 'H' level to be supplied to a non-selective word line at a pulse voltage with time width less than the readout cycle not making depend on the readout cycle, a threshold value can be prevented from being fluctuated due to the impression of the voltage of 'H' level on a control gate for a long time. In such a way, it is possible to improve the reliability for the readout operation by reducing influence due to dispersion in a threshold voltage.</p>
申请公布号 JPH027295(A) 申请公布日期 1990.01.11
申请号 JP19880156875 申请日期 1988.06.27
申请人 TOSHIBA CORP 发明人 ITO YASUO;MOMOTOMI MASAKI;IWATA YOSHIHISA;MASUOKA FUJIO;CHIBA MASAHIKO
分类号 G11C17/00;G11C16/02;G11C16/04;G11C16/08;G11C16/24;G11C16/26;G11C16/32 主分类号 G11C17/00
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