| 摘要 |
<p>PURPOSE:To improve an anti-noise property and a fast acceleration property by providing a first MOS transistor to which a first DC bias voltage is supplied and a second MOS transistor to which a second DC bias voltage less than the first DC bias voltage is supplied in a gate. CONSTITUTION:A first load circuit 30 is constituted of two P-channel MOS transistors 31 and 32 connected in series between a source voltage Vcc and a node A, and similarly, a second load circuit 60 is constituted of two P-channel MOS transistors 61 and 62 connected in series between the source voltage Vcc and a node B. And the first load means in the load circuit performs a constant current operation when a memory cell is energized and a prescribed current flows. On the other hand, the second load means is set at a non-energized state by increasing potential at a data detecting node when the memory cell is set at the non-energized state, and the potential at the data detecting node is set at a value less than the source voltage by the prescribed value. In such a way, it is possible to obtain a high operating margin for a noise and to easily attain the fast acceleration of operating speed.</p> |
