| 摘要 |
PURPOSE:To make a high speed compatible with a high integration density by a structure wherein a signal amplitude between functional blocks is made smaller than an actuating signal amplitude of individual logical blocks and is transmitted in order to eliminate a drop in a noise margin. CONSTITUTION:Logical blocks 11A, 11B are formed mainly of MOS transistors; their signal amplitude is set at 2.0V in order to secure a noise margin. A signal amplitude between functional blocks 1A, 1B and of input signals IN1 to INn is 1.2 V and is set to be smaller than the signal amplitude inside the logical blocks 11A, 11B. Accordingly, input signal level converters 12A, 12B are constituted in such a way that the signal amplitude of 1.2V is converted into 2.0V; in addition, output-signal level converters 13A, 13B are constituted in such a way that the signal amplitude of 2.0V is converted into 1.2V and that they can drive a long wiring part between the functional blocks 1A, 1B. It is desirable that the logical blocks 11A, 11B are constituted of CMOS circuits whose low- power-consumption property is especially excellent. |
