An output circuit for outputting a level shifted output signal.

摘要

An output circuit provides a high voltage output signal in response to a low voltage input signal. The output circuit includes a pull-up transistor (19) for raising the output signal substantially to a power source voltage level (VCC) and a pull-down transistor (21) responsive to the input signal for lowering the output signal substantially to the ground level (VSS). The pull-up transistor is biased by a self-bias circuit (14) triggered by a prescribed level of a control signal VG. The self-bias circuit continues to bias the pull-up MOS transistor in order to bring the output signal level to the high voltage level, even if the prescribed level period of the control signal terminates.