| 摘要 |
<p>Apparatus and method for expediting the translation of a virtual address, provided by a central processing unit, to a real address, for accessing a cache memory unit, is described. The technique relies on the fact that a procedure will typically address locations in a limited number of memory data pages during significant intervals of the procedure execution. A small associative memory is provided that, in response to at least a portion of the virtual page number, rapidly provides a trial portion of real page number. The trial portion of the real page number is used, along with the (unchanged) word portion of the address, to access the cache directory unit simultaneously with the complete translation of the virtual page number to real page number. The trial portion of the real page number is compared with the translated portion of the real page number. When the comparison is false, the location address is used to access the cache directory unit and the cache memory unit operates in typical manner. When the comparison is true, the correct cache directory unit location has been accessed, the comparison of the cache directory unit contents with the translated comparison address can be performed and access of the cache storage unit, where appropriate, can proceed.</p> |
