Semiconductor memory device

摘要

In a semiconductor memory device in accordance with the present invention, a plurality of address signals (A1 to AN) are applied to address transition detection (ATD) circuits (31 to 3N) through input buffers (11 to 1N) and according to a level change in the address signals, a pulse signal (ATDi) is applied to an inverter (5) through any of MOS field-effect transistors (41 to 4N). The input level of the inverter (5) falls rapidly in response to the rise of the output level of the ATD circuits (31 to 3N) and rises slowly by the influence of a load device (40). A chip select transition detection (CSTD) circuit (6) generates a pulse signal ( &upbar& C) in response to the change from a high level to a low level of a chip selection signal (CS) provided from a CS buffer (2). In response to the pulse signal ( &upbar& C), a p channel MOS field-effect transistor (71) is turned on and a load device (72) is connected between the power supply potential and the input of the inverter (5). As a result, the impedance therebetween is lowered and an ATD signal rises rapidly. Thus, a delay with respect to the access by the address signals can be prevented.