发明名称 Parallel analog to digital converter employing sample and hold stages
摘要 A parallel analog to digital converter and a method of processing at least two independnet signals therein are disclosed in accordance with the teachings of the present invention. The analog to digital converter has an improved sample and hold stage which, in addition to quantizing the analog signals, also multiplexes them. The sample and hold stage comprises at least two differential amplifier circuits, a latch stage, and a timing stage. Each differential amplifier circuit converts one analog input by comparing it to a reference voltage. The discrete output of the differential amplifier circuit is stored in the latch stage and outputted to an encoder. The timing circuit stage first selects one differential amplifier circuit to output its discrete signal, and then selects the latch stage to output its stored results. By sequencing through each differential amplifier circuit, the present invention effectively multiplexes the analog inputs.
申请公布号 US4893122(A) 申请公布日期 1990.01.09
申请号 US19880276258 申请日期 1988.11.25
申请人 DEUTSCHE ITT INDUSTRIES GMBH 发明人 HOEHN, WOLFGANG
分类号 H03M1/12;H03K5/08;H03K5/24;H03M1/00;H03M1/34;H03M1/36 主分类号 H03M1/12
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