| 摘要 |
PURPOSE:To shorten the preparation time of test and testing time by providing a microprocessor with a counter for increasing/decreasing a high-order address obtained from an internal address register at the time of executing a test and outputting the increased/decreased address. CONSTITUTION:The microprocessor is provided with the counter 21 for connecting the input terminal of the high-order address part 1U of the internal address register 1 to its output terminal, and when a test mode signal TST is active, the counter 21 increases the contents of the high-order address part 1U at every bus cycle and outputs the increased contents. When the signal TST is inactive, the contents of the high-order address part 1U are outputted as they are. Thereby, the increased high-order address AD1U' at every bus cycle is inputted to a table specifying decoder 3 at the time of a test mode and the contents of the whole addresses of an address conversion table can be read out within a short time by a reading instruction based upon a reading/writing signal ADRW. |
