| 摘要 |
PURPOSE:To shorten testing time by inserting many number of page cycles (cycles of page, read, modify and write) into one CAS cycle (cycle of read, modify and write). CONSTITUTION:A test-signal generating part 2 of an IC testing apparatus 1 supplies clock signals for load address strobes (RAS), write enable (WE) signals and column address strobes (CAS) into an IC under test 4. Detected signals DET are inputted into detecting and judging part 3 and tested. When the clock signals of the CAS have the operating times for page, read, modify and write modes at this time after the specifeid activating time, the effect for shortening the time can be obtained. |
