| 摘要 |
PURPOSE:To reduce the area of a diode by a method wherein a flip-flop composed of load resistors and the diodes connected in parallel with the load resistors is used as a memory cell and isolation trenches of the memory cell elements are isolated from each other and their parasitic capacitances are utilized. CONSTITUTION:A silicon oxide film 5 is provided between an N<+>-type buried layer 3 and an N<->-type epitaxial layer 4 and a P-type polycrystalline silicon layer 6. The layers 3, 4 and 6 can constitute a parasitic capacitor connected in parallel between a transistor and the anode of a diode, so that a capacitance required as a speed-up capacitor can be obtained without particular increase of an area. The P-type polycrystalline silicon layer 6 which is used as a component of the capacitor and buried in the trench is electrically isolated from polycrystalline silicon layers in other trenches. |
