| 摘要 |
PURPOSE: To reduce the reception of noise by combining a phase locked loop circuit operating to regulate a multi-phase clock whose clock speed is decided with a reference clock signal and a decoding circuit. CONSTITUTION: The multi-phase clock circuit 1 generates a four-phase clock MPC containing four parallel pulse signals. The multi-phase clock circuit 1 is constituted by a division circuit by terminals 3 and 2, delay circuit stages 7-13, a phase locked loop 15, a reset possible phase detector 17, a multi-state controller 19, a counting accumulator 21, an adjustment counting latch 23, a decoder 25 and a compensatory 27. The phase locked loop 15 is provided with a feed forward route and a feed back route. The feed back route gives accumulated multiplex bit adjustment and the feed forward route generates plural phase boundary regulation signals under the control of the accumulated adjustment counting. Thus, high clock speed can be regulated. |
