| 摘要 |
PURPOSE: To use the EPROM cell at a lower voltage to write data to the cell by providing a high capacitive coupling between a floating gate and a control gate of a memory cell transistor so as to attain the use a lower voltage during programming. CONSTITUTION: A transistor memory cell array is manufactured in a way that its embeded diffusion layer has a small sheet resistance. A general resistance of embeded diffusion layers 7, 8, 9 only is about 30Ω/cm<2> . A general sheet resistance of a silicide 36 is about 3Ω/cm<2> . A structure electrically equivalent to two conductors connected in parallel is produced by combining the silicide 36 and the diffusion layers 7, 8, 9. As a result, the combined resistance of the silicide 36 and the diffusion layers 7, 8, 9 is somewhat smaller than 3Ω/cm<2> . The resistance is reduced to about 1/10 by the addition of the silicide 36 to the diffusion layers. Thus, the EPROM memory cell is programmed by using a power supply with a small voltage.
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