| 摘要 |
PURPOSE:To reduce the area of a memory cell by a method wherein a high resistance element is provided above the gate electrode and the source region of a driving MOS transistor at least partially and, further, under an electrode for supplying a source voltage at least partially. CONSTITUTION:A driving MOS transistor DM is composed of a source region 12 buried in a semiconductor substrate 11, a drain region 14 formed on the surface of a semiconductor substrate 11 and a gate insulating film 13 and a gate electrode 15 which are buried in a trench reaching the source region 12. A high resistance element 18 is provided above the gate electrode 15 and the source region 12 of the driving MOS transistor DM and, further, directly under a source voltage (Vcc) wiring 19. By burying the source region in the semiconductor substrate completely, the source region and the other components can be laid out at the same part of a plane, so that the reduction of a memory cell area can be achieved. |
