| 摘要 |
PURPOSE:To facilitate the layout of a differential amplifying circuit by a method wherein a memory cell array is structured in a folded bit wire constitution that the differential amplifying circuit is connected between a first and a second bit wire, which compose a pair of bit wires adjacent to each other. CONSTITUTION:An erasure ('1' writing) is performed by a group unit, all word lines WL1 (WL2) are set at a voltage VPP level through a row decoder RD connected to a memory cell of a group 1 (2) an output of a control gate voltage generating circuit 1 is made VPP, and a data, which makes a potential of the differential amplifying circuit on a bit lines BL1 (BL2) side '1', is latched, whereby the potential of the bit line BL1 (BL2) is made to an 'L'. In result, electrons are injected into a floating gate of a memory transistor MQ to make its conductance lower than that of the memory transistor MQ of a dummy cell DC. |
