| 摘要 |
<p>PURPOSE:To miniaturize an economical device without characteristic deterioration by sample-holding an input data signal by means of a frequency controlled with the difference of voltages before and behind a sampling time and setting a period when the difference becomes minimum to be the phase of a maximum amplitude. CONSTITUTION:An inputted data signal (a) turns into N pieces of discrete signals (b) in a sample-holding circuit 2 by the sampling frequency signal of a voltage control oscillator 6. The signals (b) are amplified to a normal level (c) by an equalizer 3, rectified to a waveform (d) in a full wave rectifier circuit 4, and a voltage difference detection circuit 5 detects the difference of VA and VP. The frequency of the oscillator 6 is controlled by the difference. When the difference of both voltages is set to zero, the output signal is phase- synchronized with a frequency which is N times as much as a clock signal which is concerned in the data signal. A peak phase decision circuit 7 and an identification circuit 8 identify the peak part of a step waveform (e) and a regenerative clock signal (f) can be outputted while coil parts and the adjustment are set to be unnecessary.</p> |
