Circuit arrangement for generating a reference pulse

摘要

The invention relates to a circuit arrangement for generating a reference pulse which is suitable for a transmission rate of from 50 to 64000 bit/s and corresponds to an integral multiple of the transmission rate. The existing working pulse (T1) is edge-regenerated using two inverter stages (INV1, INV2) and conditioned by two parallel flip-flops (FF1, FF2) and a third flip-flop (FF3) which is connected downstream via a third inverter stage (INV3) in such a way that a reference pulse is formed on the pulse output of the third flip-flop (FF3), this reference pulse corresponding to an integral multiple of the transmission rate of from 50 to 64000 bit/s. Such circuit arrangements are used for synchronising data transmissions in communications systems such as HICOM and switch-network systems. <IMAGE>