| 摘要 |
A method and arrangement for a fully synchronized, programmable frequency divider is disclosed that exhibits a near 50% duty cycle output signal independent of the divisor, whether even or odd, and that is suitable for use in a phase-locked loop (PLL) frequency synthesizer. As described in a first embodiment, the arrangement includes a data loader 31, a counter 32, a half-period detector 33, and a synchronizer 34. Next, a fast-locking, low-noise PLL frequency synthesizer is disclosed incorporating the fully synchronized, 50% duty cycle divider, and having a reference signal generator 71-72, a phase detector 73, a controlled oscillator 74-75, and the fully synchronized, programmable frequency divider 76. In a second embodiment, a fully synchronized programmable divider is described, including a data loader 31, a counter 32, a half-period detector 33', a synchronizer 34', and an additional block 82, a half-clock period detector. Synchronizer 34' is modified to include an additional block 84, an output logic circuit, which allows for an output signal duty cycle virtually equal to 50% for odd as well as even integer divisors.
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