发明名称 |
Parallel neural network for a full binary adder |
摘要 |
A method for performing the addition of two N-bit binary numbers using parallel neural networks. The value of a first register is converted and transferred into a second register in a mathematical fashion so as to add the numbers of the first register into the second register. When the first register contains all zeros then the desired sum is found in the second register.
|
申请公布号 |
US4891782(A) |
申请公布日期 |
1990.01.02 |
申请号 |
US19870135404 |
申请日期 |
1987.12.17 |
申请人 |
UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMY |
发明人 |
JOHNSON, JOHN L. |
分类号 |
G06F7/50;G06F7/505 |
主分类号 |
G06F7/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|