Semiconductor non-volatile memory device, especially electrically programmable and erasable read-only memory device, with NAND cell structure

摘要

An EEPROM 10 includes programmable cells M11, M12 ... M4n connected to bit lines BL1, BL2 ... BLm and distributed as "NAND cell blocks" B1, B2 ..., each having: a selection transistor Qs1 coupled to a bit line BL1, a selection transistor Qs2 coupled to an earth potential Vs, and a serial arrangement of cell transistors M11, M21, M31, M41 whose control gates are coupled to word lines WL1, WL2, WL3, WL4. In read mode: a selection transistor Qs1 of a NAND cell block B1 embracing a selected memory cell M31 connects this block B1 to a bit line BL1, a circuit 100 applies a level "L" to the line WL3 coupled to the cell M31 and a pulse signal of level "H" to the other word lines. This level "H" exceeds a supply voltage and is less than the normal level "H" used in the other modes. <IMAGE>