发明名称 APPARATUS AND METHOD FOR ACCELERATING ADDITION AND SUBTRACTION OF FLOATING POINT BY ACCELERATING EFFECTIVE SUBTRACTION PROCEDURE
摘要 PURPOSE: To accelerate the effective subtraction operation of a floating point device by providing a selection circuit which controls the effective subtraction operation based on two least significant bit signals of mantissa of an operand characteristic. CONSTITUTION: When the absolute value of difference of mantissa between a floating point execution device and an operand characteristic exceeds 1, a comparatively fast procedure is applied to carry out an effective subtraction operation. If the difference is larger than 1, a longer procedure is used. A device which compares the positions of two least significant bits of mantises of two operand characteristics with each other makes it possible to use a correct operand in a longer procedure. This longer procedure is carried on until a complete difference is decided between the mantissa of two characteristics. If the procedure under execution is correct, this procedure can be carried on. If not correct, the procedure under execution is replaced with the correct one.
申请公布号 JPH01321516(A) 申请公布日期 1989.12.27
申请号 JP19880152089 申请日期 1988.06.20
申请人 DIGITAL EQUIP CORP <DEC> 发明人 BUIJIYAI MAHESHIYUWARI;SURIDAARU SAMUDORAARA;NACHIYUMU MOOSHIE GABURIEROFU
分类号 G06F7/485;G06F7/50 主分类号 G06F7/485
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