| 摘要 |
<p>A gate circuit, comprising an N-channel and a P-channel insulated gate field-effect transistor (N1, P1) whose parallel connected drain-source paths constitute an analog signal gate and a control circuit (4), connected to the respective gate electrodes, to turn on and/or turn off the two field-effect transistors (N1, P1). In order to handle signals (1) whose voltage value is higher than the maximum permissible drain-source voltage in the on-state of the N-channel field-effect transistor (N1) means are provided, in accordance with the invention, for turning on the N-channel field-effect transistor (N1) at least at a drain-source voltage below a predetermined value. In an embodiment of the invention said means comprise delay means (5) coupled to the control circuit for turning on the N-channel field-effect transistor (N1) with a delay relative to the P-channel field-effect transistor (P1). In another embodiment of the invention said means comprise switching means arranged in series with the analog signal gate, for temporarily connecting the signal gate to at least one auxiliary voltage.</p> |
