| 摘要 |
<p>PURPOSE:To prevent overlook of a true data during mis-detection by providing plural shift registers of series connection and a discriminator and comparing a start bit, a stop bit and values of leading and tail end of the shift registers. CONSTITUTION:An asynchronous serial data is inputted to plural shift registers 11a-11c for each clock and shifted, and at least the preset start bit, stop bit and values of the shift registers are compared by the discriminator 13. Only when the values are coincident, the receiver is constituted so as to fetch the data in the shift registers 11a-11c. Thus, even if the start bit is detected in mistake and a true start bit exists just after the start bit, a correct data is received surely.</p> |
