| 摘要 |
PURPOSE:To quicken the parallel serial conversion speed by comparing a phase of an input clock and that of a frequency division clock from a 1/N frequency divider circuit and controlling the output phase of the frequency division clock from the 1N frequency divider circuit so that the 1/N frequency division clock is synchronized with the input clock. CONSTITUTION:A phase control circuit 25 compares a phase of an input clock phi(0) with a phase of a frequency division clock phi(2) and the output phase of a frequency divider circuit 22 is controlled so that the median data of data to be converted DT1-DTn are read at a multiplex circuit 23 by using frequency division clocks phi(2)1-phi(2)n. Thus, the data is read at nearly the median of the data dt1-dtn in the multiplex circuit 23 by using the frequency division clocks phi(2)1-phi(2)n to improve the phase margin. Thus, the parallel serial conversion of input data is attained at high speed. |
