| 摘要 |
<p>An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer (12) is grown on a substrate (10) and contains an n-well (14), and n+ source (16) and p+ source regions (18). Shallow trenches (20, 22) are disposed in the epitaxial layer (12) and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region (24) connects the trenches (20, 22) and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer (26) of silicon dioxide on the trench walls of the gates. The p+ drain region (28), along with the filled trench gate element and the p+ source region (18), form a vertical p-channel (PMOS) trench-transistor. The n+ drain region (30), along with filled trench gate element and the n+ source (16) form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions (34) and an oxide layer (38).</p> |
