| 摘要 |
<p>A binary operator comprises a plurality of carry select adder (CSA) circuits (101a) each including a cumulative carry propagate signal generating means (106) and a cumulative carry generate signal generating means (107) and/or a plurality of block look ahead carry generator (BLACG) circuits (105a) each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means (116) and a real carry signal generating means (117). The CSA circuit (101a) does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on the three signals of a carry propagate signal (Pi), a cumulative carry propagate signal (BPi-1*) and a cumulative carry generate signal (BGi-1*) necessary for generating the presumed sum signal pair and the real carry signal (CM-1) to calculate the real sum signal (Fi). The BLACG circuit (105a) does not simultaneously generate two presumed carry signals and select and output one of the presumed carry signals, but uses a cumulative block carry propagate signal (CPM-1*), a cumulative block carry generate signal (CGM-1*) and a carry signal (CM min -m min ) to directly generate the real carry signal (CM-1). The number of circuit elements in such a binary operator is thereby greatly reduced without sacrificing high speed of computation since two presumed sum or carry signals are never generated in parallel.</p> |
