Bus stealing method for concurrent CPU and I/O processing.

摘要

This invention provides for the most amount of concurrency of I/O and CPU processing by adding an intelligent hardware circuit which controls memory bus ownership between the CPU and DMA controllers. This intelligent circuitry monitors CPU requests for main memory access and externally negates the I/O device's DREQ request signal. This in turn temporarily halts the I/O transfer, and allows the CPU to steal a bus cycle in the middle of an I/O transfer burst.