| 摘要 |
<p>A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter includes a CMOS inverter circuit (32) and a noise reduction circuit (Q3, Q4). The CMOS inverter (32) has input and output terminals (IN, OUT) and inverts an input signal (Vin) applied to the input terminal (IN) to thereby output an output signal (Vout) through the output terminal (OUT). The noise reduction circuit (Q3, Q4), which is connected to the CMOS inverter (32), rapidly passes a current (I) supplied from the CMOS inverter (32) to a low-potential power source until a potential of the output terminal (OUT) decreases to a predetermined potential in response to an increase in potential of the input signal (Vin), and slowly passes the current (I) after the potential of the output terminal (OUT) reaches the predetermined potential.</p> |
