Arrangement for bit-parallel addition of binary numbers with carry-save overflow correction

摘要

A series of adders (ADi) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (ADn-2) having the second highest significance is replaced by the carry bit of the most significant adder (ADn-1) and, in case the carry bits of the two most significant adders (ADn-1, ADn-2) are unequal, the intermediate sum bit of the most significant adder (ADn-1) is replaced by the carry bit thereof. The element ADkn-1 has the same number of transistors as the other adders AD0 . . . ADn-2.