| 摘要 |
PURPOSE: To subdivide a multistage adder/subtracter without the propagation delay of a carry signal by providing a means allowing each group of multistages to prohibit a carry propagation signal and a carry generation signal by means of the group based on a carry interruption signal and outputting another single carry signal from the group. CONSTITUTION: The multistage 2-ary adder/subtracter constitutes groups by pairing a stage (n) and a stage n+1 and each group is provided with carry propagation signal outputs Pn , Pn+1 and carry generation signal outputs Gn , Gn+1 . Then in response to the carry interruption signal, each group prohibits the propagation signals Pn , Pn+1 and generation signals Gn , Gn+1 and generates another single carry output signal from gates R, S, T, U and V. Thereby this circuit is operated as various parallel 2-ary adder or subtracter with not less than one stage without the propagation delay of the carry signal. |
