| 摘要 |
PURPOSE:To build up a data transmission system with a single line and low current consumption at a high speed without using a complicated modulator- demodulator circuit by arranging a synchronizing clock pulse and a data pulse alternately in a data format. CONSTITUTION:A 1-bit data is placed between a synchronizing pulse and that of the preceding bit, and when the data is logical '1', a data pulse is outputted and when the data is logical '0', no data pulse is outputted. With a signal 1a given at logical 'L', the transmission data is separated into a clock pulse and a data pulse by applying sampling to the data. In the presence of a data pulse, since a signal RX is set in the inverse of signal 1a at logical 'H', a Q output of a D-F/F5 goes to 'H' and in the absence of a data pulse, since no change arises in a signal RX12 for the inverse of signal 1a at logical 'H', then an output RXD of the D-F/F5 goes to logical L. |
