发明名称 ERROR DISPLAY DEVICE FOR LOGIC CIRCUIT IN TIMING VERIFICATION
摘要 PURPOSE:To achieve an easier error analysis and a shorter time by storing an error data into an error display device beforehand to display a logic circuit chart and an error state of an output signal of an element involved on a graphic terminal in a waveform. CONSTITUTION:It is assumed that logic values at inputs (a) and (b) of an NOR gate B are 1 and 0. A logic value of the input (a) changes from 1 to 0 at time t1 and when the input (b) changes from 0 to 1 at time t2 slightly delayed, an output of the gate B changes from 0 to 1 and 0 at a slight time interval (this is called as spike). An element data (element name) generating the spike, the time t2, the event 0 to 1 at that time, an event generation time t1 preceding it by one are stored as timing error data. Then, by an error display program, the timing error data is read out and a logic circuit chart near the NOR gate generating the spike is expanded to display an error in a waveform 8 on a graphic display.
申请公布号 JPH01308977(A) 申请公布日期 1989.12.13
申请号 JP19880141051 申请日期 1988.06.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 FUJITA KOICHI
分类号 G01R31/317;G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/317
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