| 摘要 |
PURPOSE:To eliminate completely the effect of peak shift by providing a phase difference storage means storing temporarily the phase difference between a data signal and a synchronizing clock signal, detecting a binary transit state of a data signal, subtracting its phase difference and a stored phase difference and introducing the result to the input of a loop filter. CONSTITUTION:A data signal (a) is supplied to a '1' detection circuit 15, from which a '1' signal (g) is generated, a phase difference storage signal (j) is supplied to a phase difference recovery circuit 19 via a phase difference storage circuit 18 storing phase difference signal (d) by a phase detection circuit 11, and a phase difference signal l is supplied to an adder integration circuit 12 by using a '0' signal (f) from a '0' detection circuit 14 detecting it that no data signal (a) exists between synchronizing clocks (c). Moreover, a shift trigger signal (h) of a data change detection circuit 16 is used to subtract a phase difference storage signal (i) stored by a phase difference storage circuit 17 and a recovered phase difference storage signal (k) stored by phase difference recovery circuit 19 and the result is given to the adder integration circuit 12. Thus, the disturbance in the synchronizing clock due to peak shift is avoided. |
