INTEGRATED CIRCUIT FOR PROCESSING ARRAY OF DIGITAL DATA AND FAST FOURIER TRANSFORM FOR BLOCK OF DIGITAL SIGNALS

摘要

PURPOSE: To execute fast processing by executing plural digital signal processing operation to the element of an operand array in response to a control signal. CONSTITUTION: An IA bus generates successive addresses necessary for collecting input data while former data is converted. A D1A bus and D2A bus generate a reading data address and a writing data address corresponding to FFT algorithm. Though a reading address pattern and a writing address pattern are the same, because proper place DIF and an FFT algorithm are adopted by MC, both patterns are separated from each other by means of a waiting time coefficient related to CE and the residual part of the device. The address sequence of a rotation coefficient memory (auxiliary data memory) are generated on an AXA bus. The successive addresses or the an address of reversed digits are generated on an OA bus to read an output data memory including data converted before. Thereby fast processing is attained.