PATTERN DATA GENERATION CIRCUIT

摘要

PURPOSE:To achieve a reduction in switching time between a parallel output and a 1 bit serial output by using a buffer memory with a variable output port to allow the selection of the 1 bit serial output without altering a port width. CONSTITUTION:A port variable buffer memory 1 is so arranged that an internal memory is divided in (n) according to the specified number (n) of output terminals to be allotted to independent I/Os (input/output terminals) and an n-bit input data is outputted in (n) bits. A 1-bit selector 3 receives various stages of count data 9 in parallel from a divided-by (m) notation counter 2 to select and output an output by 1 bit from a corresponding memory 1 connected to a specified gate circuit and produces an output as serial data 11 through an OR circuit. An output switching circuit 4 selects and outputs any one of a parallel output 8 of the memory 1 and the data 11. When the data 11 is selected, it is outputted at specified one terminal adapted to output one bit out of the output 8 while other terminal outputs are fixed at an L level.