发明名称 DECIMAL MULTIPLICATION SYSTEM
摘要 PURPOSE:To perform the decimal multiplication at a high speed by producing a desired multiple in the minimum cycle number with use of the multiple registered at present in case a multiple which is not registered in a multiple table yet and carrying out the multiplication. CONSTITUTION:The number which is segmented for each decimal digit out of a multiplier (or multiplicand) register 4 via a shifter 5 and a register flag 2 are decoded by a decoder 3. Then the corresponding multiple is read out of a multiple table 1 and added with the value of an intermediate product holding register 7 via a decimal ALU 6 for acquisition of the new value (multiplicated intermediate value) in case it is decided that said segmented value and the flag 2 are registered in the table 1. In case no registration is decided for said value and the flag 2, the optimum multiple combination is obtained for production of a desired multiple via the flag 2. Then the multiple is read out of the table 1 based on said combination and the desired multiple is produced by the ALU 6 and registered. The multiple thus obtained is added with the value of the register 7 via the ALU 6 for acquisition of the new value (multiplicated intermediate value). Thus the processing speed is improved for a decimal multiplication instruction.
申请公布号 JPH01309123(A) 申请公布日期 1989.12.13
申请号 JP19880140090 申请日期 1988.06.07
申请人 FUJITSU LTD 发明人 MASHIMA SAKAE
分类号 G06F7/52;G06F7/496;G06F7/523 主分类号 G06F7/52
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